Python Logic Simulation Library

These experiments are always unique, and each is interesting in its own way.

Can you comment on the use of asynchronous code rather than generators? For example, here's a throw-away example of a clock using generators and a syntax that's otherwise similar to yours:

  from more_itertools import take
  
  def drv_clock():
      while True:
          yield "1b1"
          yield "1b0"
  
  for x in take(10, drv_clock()):
      print(x)

I have written signal flow graphs (including feedback) using a generator-style approach, intended to prototype datapaths that are then manually translated into RTL. It's different, but not completely different.